Cryptographic hardware and embedded systems

InhaltsverzeichnisSide Channels I.Resistance of Randomized Projective Coordinates Against Power Analysis.Templates as Master Keys.A Stochastic Model for Differential Side Channel Cryptanalysis.Arithmetic for Cryptanalysis.A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis.Further Hidden Markov Model Cryptanalysis.Low Resources.Energy-Efficient Software Implementation of Long Integer Modular Arithmetic.Short Memory Scalar Multiplication on Koblitz Curves.Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 ? P.Special Purpose Hardware.SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization.Design of Testable Random Bit Generators.Hardware Attacks and Countermeasures I.Successfully Attacking Masked AES Hardware Implementations.Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.Masking at Gate Level in the Presence of Glitches.Arithmetic for Cryptography.Bipartite Modular Multiplication.Fast Truncated Multiplication for Cryptographic Applications.Using an RSA Accelerator for Modular Inversion.Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings.Side Channel II (EM).EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA.Security Limits for Compromising Emanations.Security Evaluation Against Electromagnetic Analysis at Design Time.Side Channel III.On Second-Order Differential Power Analysis.Improved Higher-Order Side-Channel Attacks with FPGA Experiments.Trusted Computing.Secure Data Management in Trusted Computing.Hardware Attacks and Countermeasures II.DataRemanence in Flash Memory Devices.Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment.Hardware Attacks and Countermeasures III.DPA Leakage Models for CMOS Logic Circuits.The “Backend Duplication” Method.Efficient Hardware I.Hardware Acceleration of the Tate Pairing in Characteristic Three.Efficient Hardware for the Tate Pairing Calculation in Characteristic Three.Efficient Hardware II.AES on FPGA from the Fastest to the Smallest.A Very Compact S-Box for AES.