Efficient MIMO Sphere Detection: algorithms and architectures

Modern wireless communications standards, such as IEEE 802.11 (WLAN), IEEE 802.16 (WiMAX), 3GPP-LTE or LTE-Advanced, define numerous transmission techniques to be supported by receiver architectures while satisfying a vast variety of stringent and most often conflicting requirements. The situation gets even more challenging with the extremely low latencies and high data rates (among other requirements) envisioned for future 5G technologies. In this context, three concepts will play a major role as key enabling factors: adaptability, efficiency and performance. In the particular context of multi-antenna spatial-multiplexing transmission, accurate detection/demodulation becomes one of the most computationally intensive processes at the receiver end. Designing efficient MIMO (multiple-input, multiple-output) detector realizations, capable of dynamically adapting to data-rate requirements, battery life, and varying channel conditions constitutes the main focus of this work. Developing adaptive, good-performing, and cost-effective MIMO detectors represents however a fairly challenging task. Ordinary low-complex approaches provide poor detection accuracy, whereas exhaustive search algorithms cannot achieve 4G/5G data rates with reasonable hardware complexity. In this regard, the so-called sphere detector, a tree-search-based detection technique, has arisen as the only approach capable of conveniently trading adaptability, efficiency and performance. Iterative detection-and-decoding enables a dramatic improvement of the communication’s reliability by exchanging soft information between the detector and the decoder, at the cost of increasing the receiver’s complexity. One of the major challenges in this context is represented by the distortive effect that the soft information causes on the search ordering, which represents a critical aspect affecting the detection accuracy and complexity of tree-search algorithms. In this regard, characterizing the influence of the soft information on the detection process and developing strategies which alleviate the inherent complexity and performance loss drawbacks constitute a major objective of this work. Among other strategies, a novel enumeration mechanism which determines the optimal symbol ordering while incurring a much lower computational effort than state-of-the-art approaches is proposed and evaluated. Besides addressing the mentioned challenges from the algorithmic perspective, developing suitable architectures which lead to efficient MIMO detector realizations represents an additional major goal. In order to satisfy the standard-defined high throughput requirements while complying with stringent area and power consumption restrictions (present in e. g., pico/femtocell base stations, sensor networks or mobile terminals), the focus is laid onto the application-specific instruction-set processor (ASIP) paradigm. To assess the true hardware complexity and efficiency of the proposed VLSI designs, their physical characteristics are analyzed (including on-chip measurements) and compared to the state-of-the-art. Owing to the reported low resource-requirements and the high adaptability in terms of energy and performance, the proposed detector solutions are shown to be applicable to a wide variety of network elements and support numerous communications standards.