Robustness and Usability in Modern Design Flows

More about the book

Focusing on the challenges in designing and verifying integrated circuits, this book analyzes current methodologies and identifies deficiencies, proposing enhanced solutions. It offers a comprehensive tool flow for Synthesis for Testability of SystemC descriptions, enabling fully testable circuits with efficient test pattern generation. Additionally, it introduces a new paradigm for formal design verification based on design understanding and automated property generation. Empirical evaluations of these techniques demonstrate improved automation and robustness in the design flow.