System-level modeling, analysis and optimization of DRAM memories and controller architectures

Abstract The maximum memory bandwidth for external memory is smaller than the bandwidth requirements of modern high-performance Computers and embedded Systems. This increasing gap, the so-calied memory wall, limits the Performance of today's data intensive applications. The external main memory is realized with Dynamic Random Access Memory (DRAM) for many decades. Recently, three-dimensionally stacked DRAM memories, e. g. Wide I / O, HMC and HBM, have been introduced, which are a promising solution to today's bandwidth and energy problems. By means of TSVs, these memories reduce the distance to the proces, sors from centimeters to micrometers. This new technology promises a higher available bandwidth due to a larger number of data signals and a significant increase in energy efficiency compared to common DDR DRAMs. This combination of high bandwidth and low power consumption is ideal for embedded Systems as well as high Performance Computing. These new DRAM memories raise new challenges with respect to the design Space, power consumption, reliability and memory Controllers. To tackle the mentioned challenges we present a holistic exploration framework that consists of models that are reflecting the DRAM functionality, power, temperature and retention time errors. With this framework we are able to explore the design space and analyze the limiting parameters and discover potential issues in advance. By means of this holistic framework we present several contributions to the DRAM Subsystem with respect to refresh and power-down management, as well as DRAM reliability and memory Controller architecture.